Texas Instruments OMAP5912 Reference Manual page 206

Clock Generation and Reset Management
Table 65. MPU Idle Enable Control Register 2 (ARM_IDLECT2) (Continued)
Bit Name
2 EN_PERCK
1 EN_XORPCK
0 EN_WDTCK
For reserved bits, reading gives undefined values. Writing to has no effect.
Note:
148 OMAP3.2 Subsystem
Base Address = 0xFFFE CE00, Offset = 0x08
Function
Enables the external peripheral clock.
0: The external peripheral clock ARMPER_CK is
stopped.
1: The external peripheral clock ARMPER_CK is
active and can be stopped depending on the
IDLLPER_ARM bit.
Enables the clock of the OS timer connected to MPU
TIPB and the external reference peripheral clock.
0: The OS timer clock and the external peripheral
clock are stopped.
1: The OS timer clock and the external peripheral
clock are active and can be stopped depending on
the IDLXORP_ARM bit of ARM_IDLECTL1.
Enables the clock of the timer/watchdog connected to
MPU TIPB.
(When the timer/watchdog is configured as watchdog
timer, the clock is never shutdown regardless the
value of IDLWDT_ARM and EN_WDTCK).
0: The timer/watchdog clock is stopped.
1: The clock supplied to timer/watchdog clock is
active and can be stopped depending on the
IDLWDT_ARM bit of ARM_IDLECTL1.
R/W Reset
R/W 1
R/W 0
R/W 0
SPRU749A