Texas Instruments OMAP5912 Reference Manual page 998

Table 15. OMAP3.2 Timing Parameters (Continued)
System DMA clock (ns)
DSP DMA clock (ns)
CCP clock (ns)
† Timing parameters are calculated for a mobile DDR.
‡ Timing parameters are calculated for a standard SDRAM.
Table 16. Peripheral Access Time Calculations
MPU to boot Burst
ROM* read/write,
32b read,
16/8b read
MPU to Burst
secure read/write,
ROM* 32b read,
16/8b read
MPU to Burst
secure read/write,
RAM* 32b
read/write,
16/8b
read/write
† This latency value includes the following:
− Initial latency: from enable to 1st transaction
− Pipeline latency: from source to destination
− Close latency: from last acknowledge to release of the channel
− For the normal and dedicated P-channel case
‡ Page open: external SDRAM is a mobile DDR
§ 51 equivalent TC cycles = 19 TC cycles plus 16 CCP interface cycles
SPRU758A
On-Chip/Off-Chip Memory and Peripheral Access Latencies
DMA
CCP
Table 16 lists access time calculations for different class of peripherals.
Burst Read
First Data
ns Initiato
r
cycles
70 14
70 14
70 14
10
5
20
Single Read
Line
Fill
ns Initiator ns
cycles
185 37 70
185 37 70
185 37 70
Peripheral Interconnects
CCP cycle
Single Write
Initiato ns Initiator
r cycles
cycles
14
14
14 70 14
47