Table of Contents
Advertisement
Clock Generation and Reset Management
System DMA Idle Control
MPU TIPB Bridges Idle Control
4.3.4
External Device Power Control
138
OMAP3.2 Subsystem
The TC_CK restarts upon:
J
An MPU or DSP interrupt request
J
A DMA request
J
L3_OCPI_EN pin set to logic 1 (enables restarting of the clock to L3
OCP initiator bus)
The system DMA employs a built-in power-saving mechanism. The clock is
only requested to the clock generator when DMA transfers are occurring.
The DMA clock can enter idle mode if one of the following conditions is true:
-
DMACK_REQ = 1 and there are no DMA requests.
-
DMACK_REQ = 0, the MPU clock is in idle, IDLIF_ARM = 1, there are no
DMA requests, and the DMAIDLE_ACK signal is high.
The TIPB bridges can enter idle mode only when all of the following conditions
are true:
-
MPU is set in idle mode.
-
The idle interface bit IDLIF_ARM of ARM_IDLECT1 register is set to
logical 1.
-
There are no system DMA requests to the TIPB.
-
There is no posted write (that is, posted write buffers are empty).
The FLASH.RP signal is an output pin that allows the reset/power-on control
sequences of external devices such as flash memory.
Whenever the traffic controller enters the idle mode, the FLASH.RP pin
switches from a high to a low level, allowing external components to be turned
off. When a wake-up condition is detected, the pin is switched back to a high
level and restores power to external devices.
Setting the bit REPWR_EN of ARM_EWUPCT to logical 0 enables this
capability. At reset, this is disabled.
To allow the external device/component voltage to stabilize (ramp-up) when
the power-down mode is released, the external power control is implemented
SPRU749A
Advertisement
Chapters
Table of Contents
