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3.4
OCP-I Programming
SPRU749A
The OMAP 3.2 OCP external initiator port is an interface intended to connect
an external master device to the OMAP 3.2 platform. The OMAP 3.2 core
appears as a slave, and its entire memory map, including TIPB peripherals,
is accessible. The interconnect bus is compliant with the OCP specification.
The OCP initiator is capable of single transfers in 8, 16, and 32 bits and burst
mode transfers in 32 bits.
OCP-I provides access to the following OMAP targets:
-
EMIFS (external slow memories)
-
EMIFF (external fast memories)
-
OCPT1
-
OCPT2
-
Multibank OCPT1/2
-
MPUI (not part of the TC; see section 5, MPUI)
-
MPU private TIPB bridge (not part of the TC; see section 7, TIPB Bridge)
-
MPU public TIPB bridge (not part of the TC; see section 7, TIPB Bridge)
Figure 41 shows the OCP-I block diagram.
Traffic Controller
OMAP3.2 Subsystem
89
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