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SPRU750A
The DSP MMU contains a 32-entry translation lookaside buffer (TLB) that
holds translations and permissions for current pages. This TLB is often
managed statically by the MPU OS; but the MMU also includes hardware table
walking logic, as in the MPU, to autonomously traverse the page table on a
TLB miss. In this case, the TLB can be seen as a cache of recently used page
table entries.
The format of the page table and TLB entries of the DSP match those of the
MPU.
The DSP subsystem internal memory is analogous to the DSP cache; it is
directly addressed by the processor (logically addressed), and therefore no
translation is carried out. The one difference between the DSP and MPU
subsystems is that within the DSP subsystem no permission checks are
carried out when the DSP accesses its internal memory.
If the DSP MMU requires software intervention, the MPU is responsible for
servicing the event; DSP MMU errors are signaled to the MPU with a dedicated
interrupt. The DSP MMU is programmed by the MPU.
The main goals of the MMU are:
-
To translate the DSP internal (logical) addresses into OMAP (physical)
addresses
-
To prevent the DSP software from making invalid accesses to system
memory
Figure 11 shows the relation between the major blocks of the MMU.
Subsequent sections describe the functions of each of the blocks.
DSP Memory Management Unit
DSP Subsystem
59
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