Texas Instruments OMAP5912 Reference Manual page 311

Multimedia processor device overview and architecture

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DSP Subsystem

The private TIPB bridge provides a preconfigured bus interface to

peripherals residing on the the DSP private TIPB.

The public TIPB bridge provides a user-configurable interface to

peripherals on the DSP public TIPB. It includes functions to tailor the

interface timing to the complement of peripherals operating at a given

The TIPB bridge also contains registers to control and monitor the DSP

subsystem idle state. The DSP TIPB bridge can be configured using the

following registers in DSP I/O space:

Control mode register (CMR): DSP I/O word address is 0x0000.

Idle control register (ICR): DSP I/O word address is 0x0001.

Idle status register (ISTR): DSP I/O word address is 0x0002.

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