Texas Instruments OMAP5912 Manuals

Manuals and User Guides for Texas Instruments OMAP5912. We have 2 Texas Instruments OMAP5912 manuals available for free PDF download: Reference Manual

Texas Instruments OMAP5912 Reference Manual (2144 pages)

Multimedia Processor Device Overview and Architecture

Brand: Texas Instruments | Category: Computer Hardware | Size: 8.84 MB

Figures

11
- Table of Contents
  11
- Top-Level OMAP5912
  14
- OMAP5912 Top-Level Detailed Diagram
  20
- MPU Private Peripherals
  21
- DSP Private Peripherals
  21
- MPU Shared Peripherals
  22
- DSP Shared Peripherals
  22
- MPU/DSP Statically Shared Peripherals
  23
- MPU/DSP Dynamically Shared Peripherals
  23
- OMAP5912 Dedicated Modules
  24
- OMAP5912 Test Modules
  25
- OMAP3.2 Gigacell
  28
- LDCONV Integration
  30
- Compactflash Interface
  31
- HDQ/1-Wire Overview
  33
- MCSI1 Interface
  34
- MCSI2 Interface
  35
- 6X5 Keyboard Connection
  37
- UART Clock Scheme
  38
- Available I/Os Per UART
  39
- Mcbsp Interface with I2S-Compliant External Codec
  40
- Mcbsp Interface with Communication Processor
  41
- Mcbsp3 Interface Connected to Optical Device
  42
- USB OTG Integration at System Level
  44
- CCP Internal Block Diagram
  47
- CMT-APE Interchip Communication
  48
- Sossi Internal Block Diagram
  49
- MMC/SDIO Block Connection
  50
- Event Captures for Peripheral Wake-Up Capability
  53
Table of Contents

67
Table of Contents

272
- Architecture Overview
  278
- DSP Core
  280
- Tms320C55X DSP CPU Overview
  281
- On-Chip Memory
  282
- Power Conservation
  282
- CPU Overview
  283
- Hardware Acceleration Modules
  283
- DSP Memory
  285
- Instruction Cache
  286
- Internal Memory
  286
- Cache Memory Organization
  287
- Instruction Cache Structure
  288
- Ramset Memory Organization
  288
- Instruction Cache Operation
  290
- Ramset Structure
  290
- Instruction Cache Configuration
  291
- ST3 Control Register (ST3)
  291
- I/O Mapped Cache Control Registers
  292
- LVB and LRU Status Registers
  295
- Cache Functional Configuration
  296
- Enable and Disable I-Cache
  296
- I-Cache Operations
  296
- Ramset Functional Configuration
  296
- Configuration Examples
  297
- Example of Configuring and Enabling Direct Map with One Ramset
  297
- Example of Configuring and Enabling Two-Way Set-Associative Cache
  297
- Freeze Mode
  297
- Flush I-Cache
  298
- Flush a Ramset
  299
- Flush Cache Line
  299
- Flush the N-Way I-Cache
  299
- Hit Time
  300
- I-Cache Performance
  300
- Miss Penalty
  300
- Emulation Mode
  301
- Emulator Visibility
  301
- Software Breakpoint Detection
  301
- System Memory
  301
- Memory Map
  302
- Peripheral Register Addresses
  306
- TIPB Bridge
  310
- Control Mode Register
  313
- MPU Interface
  317
- HOM/SAM Change Outside of Reset
  319
- ST3-HOM_P Bit (Bit 8)
  319
- ST3-HOM_R Bit (Bit 9)
  319
- EMIF Global Control Register
  320
- External Memory Interface
  320
- Description
  321
- DSP Memory Management Unit
  321
- EMIF Global Reset Register
  321
- Address Translation
  323
- Translation Process
  324
- Coarse
  327
- Page Table Format
  327
Table of Contents

364
- Overview
  368
- Low-Dropout (LDO) Voltage Regulator
  369
- OMAP5912 Integration
  369
- 96-Mhz APLL
  370
- Analog Phase-Locked Loop
  371
- Omap3.2 Dpll
  371
- Application Guidelines
  374
- Fast Lockup
  374
- Bmode Switching
  375
- Missing Input Clock
  375
- Omap3.2 Dpll
  375
- Features
  376
- Functional Description
  376
- Low-Dropout Voltage Regulator
  383
- Timing Diagrams
  386
- OMAP5912 Clock Architecture
  387
- External System Clock with Reset Mode 0
  388
- Reset Modes and Clocking Options
  388
- External 32-Khz Clock with Reset Mode 0
  389
- Using the Internal Oscillator for a 32-Khz Clock with Reset Mode 0
  390
- Using the Internal Oscillator for the System Clock with Reset Mode 0
  390
- External System Clock with Reset Mode 1
  391
- External 32-Khz Clock with Reset Mode 1
  392
- Using the Internal Oscillator for a 32-Khz Clock with Reset Mode 1
  393
- Using the Internal Oscillator for the System Clock with Reset Mode 1
  393
- Clock Distribution in OMAP5912
  394
- Clock Inputs to ULPD
  394
- OMAP 3.2 Clocks
  397
- Clock Distribution to Peripherals
  399
- Peripheral Clocks
  401
- Peripheral Module Clocking
  401
- Clock Gating in ULPD
  406
Table of Contents

421
- Reset Architecture
  424
- Reset Modes and Clocking Options
  424
- Resets
  425
- Global Reset
  426
- RTC Split Power
  426
- OMAP 3.2 Resets
  430
- Peripheral Resets
  432
- Peripheral Reset Table
  434
- Input/Output
  441
- Configuration
  443
- Configuration Register Capabilities
  444
- Pin Multiplexing and Pullups/Pulldowns
  445
- Pin Multiplexing Considerations with Respect to RESET_MODE
  445
- Configuration of USB Ports 0, 1, and 2
  446
- Multiplexing Exceptions with USB Host Client
  446
- Procedure for Setting the Pin Multiplexing
  447
- Parallel Observability During Functional Mode
  448
- OMAP5912/5910 Software and Hardware Compatibility
  450
- Configuration Registers
  452
- External Interface Descriptions
  508
- External Interfaces
  508
- Duplicated Interfaces
  509
- Boot Mode Control and EMIFS Multiplexing Control Generation
  511
- Reset/Boot Overview
  511
- Configuration of Interfaces in Internal Boot ROM
  512
- OMAP Device Identification Registers
  514
Table of Contents

527
- ULPD Features
  533
- Ultralow-Power Device
  533
- Overview
  534
- ULPD Input Clock Sources
  536
- ULPD Setup Counters
  536
- Big Sleep Mode
  537
- Deep Sleep Mode
  537
- Power Modes
  537
- Awake Mode
  538
- Behavior of LOW_PWR
  538
- External Clock and Voltage Supply Control
  538
- Behavior of LOW_PWR
  539
- Leakage Current Management
  539
- Low-Voltage Operation at Reduced Clock Frequency
  540
- Transitions between Power Modes
  541
- Power-On Transition to Deep Sleep Mode
  543
- Transition from Deep Sleep to Big Sleep Mode
  543
- Transitions from Deep Sleep Mode
  543
- Transition from Deep Sleep to Awake Mode
  545
- Transition from Big Sleep Mode to Deep Sleep Mode
  549
- Transitions from Big Sleep Mode
  549
- Transition from Awake Mode to Deep Sleep Mode
  550
- Transition from Big Sleep Mode to Awake Mode
  550
- Transitions from Awake Mode
  550
- Transition from Awake Mode to Big Sleep Mode
  551
- ULPD Output Clocks
  552
- Device Power up
  560
- Power-Up and Reset Management
  560
- Generic Power-Up Sequence in Oscillator Mode
  561
- Power-Up Sequence in External Clock Mode
  562
- OMAP3.2 Reset Generation
  563
- ULPD Reset Inputs
  563
- OMAP3.2 Embedded LDO for DPLL[3] Control
  564
- Analog Phase-Locked Loop Control
  565
- Battery Failed Interrupt
  565
- 32-Khz Oscillator Calibration
  567
- Bad Devices
  567
- ULPD Interrupt Generation
  568
- ULPD Registers
  568
- Power Domains
  585
- Power System Overview
  585
- Clock Domain
  588
- DPLL1 Clock
  590
- DSP/MPU/TRAFFIC Clocks
  590
- Power Management User Services
  590
- Power Services
  590
- Static Clock Management
  590
- DSP (MGS3) Clocks Management
  593
- Global Power Management
  593
- Local Power Management
  595
- Rng Clocks
  598
- Total RNG Shutdown
  598
- Partial RNG Shutdown: Input Clock Cut off
  599
- Total RNG Shutdown: Reset RNG Module
  600
- Autogating Mechanisms
  601
- Dynamic Management
  601
- Externals Clocks
  601
- OMAP3.2 Autogating
  601
- OMAP5912 Peripherals Autogating
  601
- MGS3/DSP Autogating
  602
- Introduction
  603
- ULPD Power Modes Management
  603
- ULPD Mechanisms Description
  604
- ULPD Mode Descriptions
  604
- Control of External Clock and Voltage Supplies
  606
- Transitions between ULPD Modes
  607
- Power Domain Management
  608
- RTC Domain Management
  608
- DSP Domain Management
  610
- Dynamic Voltage Scaling
  611
- Low Voltage with Chip Totally Shut down
  611
- Oscillator Clock Mode
  611
- External Clock Mode
  612
- Low Voltage with Chip Running at Reduced Clock Frequencies
  613
- OMAP5912 Power Modes
  613
- OMAP5912 Power Mode Transitions
  615
- OMAP5912 Power Management Software User Guide
  621
Table of Contents

628
- DMA Overview
  637
- GDMA Handlers
  637
- MPU GDMA Handler
  637
- MPU GDMA Handler Configuration
  641
- DSP GDMA Handler
  646
- DSP GDMA Handler Configuration
  648
- System DMA
  652
- Functional Description
  654
- System DMA Controller Simplified Block Diagram
  654
- Logical Channel Types
  655
- OMAP 3.2 System DMA Instances
  656
- Synchronized Channel
  657
- Physical Ports
  659
- Port Channel Scheduling
  661
- Time Sharing Access on a System DMA Port
  661
- Logical Channel Scheduling
  662
- Logical Channel Priorities
  663
- Logical Channel Scheduling Scheme
  663
- Logical Channel Interleaving for Synchronized Transfers
  664
- Logical Channel Interleaving on Channel Boundary with the same Priority
  664
- Linking Logical Channels
  665
- Logical Channel Preempting
  667
- Addressing Modes
  668
- Data Alignment
  669
- Constant Addressing Mode
  670
- Post-Incremented Addressing Mode
  670
- Post-Incremented Addressing Mode Memory Accesses
  671
- Single-Indexed Addressing Mode
  671
- Single-Indexed Addressing Mode Memory Accesses
  672
- Double-Indexed Addressing Mode
  673
- Double-Indexed Addressing Mode Memory Accesses
  674
- Data Packing and Bursting
  675
- Interrupt Generation
  681
- DMA IDLE Modes
  683
- Dynamic Idle Mode
  683
- System DMA Interrupt Mapping
  683
- System IDLE Request
  684
- DMA Debug State
  685
- DMA Packed Channel Status Register for Compatible Mode
  690
- Dsp Dma
  745
- DSP DMA Controller Features
  747
- Channels and Port Accesses
  750
- Channel Autoinitialization
  751
- MPUI Access Configurations
  752
- Service Chain
  753
- Service Chain Example
  755
- Units of Data
  757
- Start Address
  758
- Start Addresses in a Channel
  758
- Start Address in I/O Space
  759
- Updating Addresses in a Channel
  760
- Addressing Modes
  761
- Constant Addressing Mode
  762
- Double-Indexed Addressing Mode
  763
- Post-Incremented Addressing Mode
  763
- Single-Indexed Addressing Mode
  763
- Data Packing
  764
- Bursting
  765
- Data Alignment
  767
- Synchronizing Channel Activity
  767
- Read Synchronization Vs. Write Synchronization
  768
- Checking the Synchronization Status
  769
- Dropped Synchronization Events
  769
- Monitoring Channel Activity
  769
- Channel Interrupt
  770
- Time-Out Conditions
  771
- DMA Transfer Latency
  772
- DMA Controller Configuration Registers
  773
- DMA Power Reduction
  773
- Emulation Modes
  773
- DATA_TYPE Bit
  782
- Channel Source Start Address
  793
- Channel Destination Start Address
  794
- DSP DMA Programming Guidelines
  799
- Transfer Source and Destination
  799
- Transfer Start
  799
- Autoinitialization
  800
- Addressing Modes
  801
- Data Packaging and Bursting
  802
- Data Alignment
  803
- Interrupt Generation
  803
- DMA Operation in Power-Down Mode
  804
- Memory Space Issues
  804
Introduction/Memory Interfaces for the Emifs

815
- Introduction
  821
- SDRAM Interface
  821
- OMAP1612 Stacked DDR Support
  822
- Asynchronous and Synchronous Burst Memory Interface (EMIFS)
  824
- Memory Interfaces for the EMIFS
  825
- Hardware NAND Flash Controller
  826
- Read Operation
  831
- Write Operation
  831
- Multiplane
  832
- Erase Operation
  833
- Restriction in Addressing with Multiplane Page Program
  833
Table of Contents

902
- Interrupt Overview
  907
- DSP Interrupt Mapping
  909
- DSP Level 2 Interrupt Handler
  910
- DSP Level 2 Interrupt Mapping
  910
- MPU Interrupt Mapping
  912
- ARM926EJS Level 2 Interrupt Mapping
  914
- Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
  917
- Functional Description
  918
- Edge-Triggered Interrupts
  920
- Interrupt Processing Sequence
  920
- Level-Sensitive Interrupts
  920
- Interrupt Handler Sleep Mode
  921
- Interrupt Latency
  921
- External Interrupt Asynchronous Path
  922
- Force Wake-Up Mode
  922
- Going to Sleep
  922
- Smart Idle Mode
  922
- Waking up
  922
Table of Contents

960
- Shared Peripherals
  965
- Layer 4 Interconnect
  971
- Protocols
  974
- Bus Allocation
  975
- MPU/DSP TIPB Bridge to Peripherals
  976
- Peripherals to MPU/DSP TIPB Bridge
  976
- Reset Methodology
  984
- TIPB-OCP/OCP-TIPB Wrapper for USBOTG
  984
- Peripheral Instantiation
  986
- TIPB Router
  986
- OCP Interconnect
  988
- 1X OCP Master Port
  992
- Address Space
  992
- Arbiter Block
  992
- Buffer Block
  992
- Introduction
  993
- SSI Interconnect
  993
- OCP to VIA Asynchronous Bridge
  994
- Decode
  995
- DMA and Interrupt Formatter
  995
- OCP to VIA Synchronous Bridge
  995
- Clock and Reset Module
  996
- OCPI REGISTERS (MPU Address: FFFE:C320)
  996
- OCPT REGISTERS (MPU Address: FFFE:CC00)
  996
- On-Chip/Off-Chip Memory and Peripheral Access Latencies
  996
- Power Saving Modes
  996
- Programming Model
  996
Table of Contents

1007
- 32-Bit Watchdog Timer General Overview
  1013
- Posted and Nonposted Writes
  1013
- Overflow/Reset Generation
  1014
- Reset Context
  1014
- Triggering New Reload
  1014
- Prescaler Value/Timer Reset Frequency
  1015
- Accessing Watchdog Registers
  1016
- Modifying WCRR, WLDR, and Prescaler Ratios
  1016
- Start/Stop Command
  1016
- WCRR Access Restriction
  1016
- Watchdog Module under Emulation
  1017
- Watchdog Timer Registers
  1017
- 32-Khz Watchdog Timer
  1023
- DSP and MPU os Timer Start and Stop
  1024
- OMAP3.2 Operating System Timer
  1024
- DSP and MPU os Timer
  1025
- DSP and MPU os Timer Input Clocks
  1025
- Reading os Timer Values
  1025
- Input Clock Enable
  1026
- Timer Interrupts
  1026
- DSP 32-Bit os Timers
  1028
- OS Timer Registers
  1028
- Timer Programming
  1028
- MPU 32-Bit os Timers
  1031
- Dual-Mode Timer
  1033
- Description
  1035
- Mode Functionality
  1036
- Capture Mode Functionality
  1037
- Compare Mode Functionality
  1037
- Prescaler Functionality
  1037
- Pulse-Width Modulation
  1038
- Timer Interrupt Control
  1039
- Sleep Mode Request and Acknowledge
  1040
- Timer Counting Rate
  1041
- Wake-Up Line Release
  1041
- Accessing Registers
  1042
- Dual-Mode Timer under Emulation
  1042
- Programming Timer Registers
  1042
- Reading Timer Registers
  1042
- Software Non-Write Posting Synchronization Mode
  1043
- Software Write Posting Synchronization Mode
  1043
- Writing Timer Registers
  1043
- Write Mode Selection
  1044
- Dual-Mode Timer Registers
  1045
- Implementation
  1054
- 32-Khz Synchronized Timer
  1055
- Functional Description
  1055
- Reading the Timer
  1055
- 32-Khz Synchronization Timer Registers
  1056
- Countdown Operation
  1058
- Operating System Timer
  1058
Table of Contents

1070
- Arbitration_Lost (AL)
  1139
- Reset Done (RDONE)
  1139
- Data Count (DCOUNT)
  1141
- Transmit/Receive FIFO Data Value (DATA)
  1141
- Soft Reset (SRST)
  1142
- I2C Module Enable (I2C_EN)
  1143
- Big Endian (BE)
  1144
- Master/Slave Mode (MST)
  1144
- Start Byte (STB)
  1144
- Expand Address (XA)
  1145
- Transmitter/Receiver Mode (TRX)
  1145
- Start Condition (STT)
  1146
- Stop Condition (STP)
  1146
- Own Address (OA)
  1147
- Slave Address (SA)
  1147
- SCL Low Time (SCLL)
  1148
- SCL High Time (SCLH)
  1149
- Free Running Mode after Breakpoint (FREE)
  1150
- System Test Enable (ST_EN)
  1150
- Set Status Bits (SSB)
  1151
- Configure Slave Address and Data Counter Registers
  1153
- Initialization Procedure
  1153
- Initiate a Transfer
  1153
- Main Program
  1153
- Module Configuration before Enabling the Module
  1153
- Poll Receive Data
  1153
- Programming Guidelines
  1153
- Interrupt Subroutines
  1154
- Poll Transmit Data
  1154
- Flow Diagrams
  1155
- Microwire Interface
  1164
- Microwire Registers
  1164
- Protocol Description
  1171
- Example of Protocol Using a Serial EEPROM (XL93LC66)
  1172
- Read Cycle
  1172
- Write Cycle
  1173
- Example of Protocol Using an LCD Controller (COP472-3)
  1174
- Loading Sequence
  1175
- Example of Protocol Using Autotransmit Mode
  1176
- Example of Autotransmit Mode with DMA Support
  1178
- Communication Protocol
  1179
- Configuration Parameters
  1179
- Multichannel Serial Interfaces
  1179
- Slave/Master Control
  1179
- Continuous/Burst Mode
  1180
- Normal/Alternate Frame Synchronization
  1180
- Short/Long Framing
  1180
- Single-Channel/Multichannel
  1180
- Channel Used
  1181
- Frame Size
  1181
- Normal/Inverted Clock
  1181
- Normal/Inverted Frame Synchronization
  1181
- Word Size
  1181
- MCSI Configuration
  1182
- Transmission Clock Frequency
  1182
- Interface Management
  1183
- Interrupts Generation
  1183
- Stop MCSI
  1183
- Receive Interrupt
  1184
- Transmit Interrupt
  1184
- Frame Duration Error Interrupt
  1185
- DMA Channel Operation
  1187
- Interrupt Programming
  1187
- Receive DMA Transfers
  1188
- Transmit DMA Transfers
  1188
- Interface Activation
  1189
- Start Sequence
  1189
- Functional Mode Timing Diagrams
  1190
- Single-Channel/Alternate Long Framing
  1190
- Software Reset
  1190
- Stop Sequence
  1190
- Multichannel/Normal Short Framing/Channel4 Disable
  1191
- Single-Channel/Alternate Long Framing/Burst
  1191
- Single-Channel/Alternate Short Framing/Continuous/Burst
  1191
- Multichannel/Alternate Long Framing/Continuous/Burst
  1192
- Multichannel/Normal Short Framing/Burst
  1192
- Single-Channel/Normal Short Framing
  1192
- Single-Channel/Normal Long Framing
  1193
- Single-Channel/Normal Long Framing/Burst
  1193
- Single-Channel/Normal Short Framing/Burst
  1193
- Single-Channel/Alternate Short Framing
  1194
- Single-Channel/Alternate Short Framing/Burst
  1194
- Single-Channel/Normal Long Framing/Continuous
  1194
- MCSI Register Descriptions
  1195
- MCSI1 and MCSI2
  1202
- MCSI1 Pin Description
  1202
- MCSI1 Interrupt Mapping
  1203
- MCSI1 DMA Request Mapping
  1204
- MCSI2 Pin Description
  1204
- MCSI2 Interrupt Mapping
  1205
- Uarts
  1207
- Main Features
  1208
- Irda Functions
  1209
- Uart/Modem Functions
  1209
- Control and Status Registers Description
  1211
- UART Irda Registers Mapping
  1211
- Interrupt Enable Register (IER)
  1221
- UART Modes IER
  1221
- Irda Modes IE
  1222
- Divisor Latches (DLL, DLH)
  1226
- Received Frame Length Register (RXFLL, RXFLH)
  1232
- Transmit Frame Length Register (TXFLL, TXFLH)
  1232
- Status FIFO Register (SFREGL, SFREGH)
  1234
- Different Modes of Operation
  1238
- SIR Mode
  1239
- UART Modes
  1239
- Frame Format
  1240
- Abort Sequence
  1241
- Asynchronous Transparency
  1241
- Pulse Shaping
  1241
- Decoder
  1242
- Encoder
  1242
- IR Address Checking
  1243
- MIR Mode
  1243
- MIR Transmit Frame Format
  1243
- MIR Encoder/Decoder
  1244
- SIP Generation
  1244
- FIR Mode
  1245
- Functional Description
  1245
- Trigger Levels
  1245
- Interrupts
  1246
- UART Mode Interrupts
  1246
- Irda Mode Interrupts
  1247
- FIFO Interrupt Mode Operation
  1248
- Wake-Up Interrupt
  1248
- DMA Signaling
  1250
- FIFO DMA Mode Operation
  1250
- FIFO Polled Mode Operation
  1250
- DMA Transfers (DMA Mode 1, 2, or 3)
  1251
- Sleep Mode
  1254
- UART Modes
  1254
- Break and Time-Out Conditions
  1255
- Idle Modes
  1255
- Irda Modes
  1255
- Time-Out Counter
  1255
- Break Condition
  1256
- Omap5912 Spru755B
  1617

Texas Instruments OMAP5912 Reference Manual (234 pages)

Multimedia Processor DSP Subsystem

Brand: Texas Instruments | Category: Computer Hardware | Size: 0.99 MB

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