Texas Instruments OMAP5912 Reference Manual page 151

Table 8. OCP Priority Registers 1 and 2(OCPT1_PRIOR and OCPT2_PRIOR)
(Continued)
Bit Name
6:4 DSP_PRIORITY
3
2:0 ARM_PRIORITY
Table 9. OCP-T1 and OCP-T2 Priority Time-Out Registers 1 (OCPT1_PTOR1 and
OCPT2_PTOR1)
Bits Field
31:8 RESERVED
7:0 DMA
Table 10. OCP-T1 and OCP-T2 Priority Time-Out Registers 2 (OCPT1_PTOR2 and
OCPT2_PTOR2)
Bits Field
31:24 RESERVED
23:16 DSP
SPRU749A
Base Address = 0xFFFE CC00, Offsets = 0x00 and 0xD0
Function
Number of consecutive accesses allowed for DSP
Reserved
Number of consecutive accesses allowed for MPU
The OCP target priority registers (OCPTx_PRIOR) allow the target to give
consecutive accesses to a host when the host is granted the OCP target.
The MPU and DSP can have from 1 to 8 consecutive accesses. The DMA and
the OCP initiator can have 1 to 16 consecutive accesses, depending on the
content of corresponding bits in their priority registers.
Base Address = 0xFFFE CC00, Offsets = 0xA0 and 0xD4
Description
Reserved. To ensure software compatibility,
reserved bit should be written to 0.
Number of TC_CK cycles that DMA must wait in
low-priority queue before going to high-priority queue
Base Address = 0xFFFE CC00, Offsets = 0xA4 and 0xD8
Description
Reserved. To ensure software compatibility, reserved
bit should be written to 0.
Number of TC_CK cycles that DSP must wait in
low-priority queue before going to high-priority queue
Traffic Controller
R/W
R/W
R/W
R/W
R/W 0x000000
R/W
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
000
000
Reset
0x00
Reset
0x00
0x00
93