Texas Instruments OMAP5912 Reference Manual page 199

4.4 Registers
4.4.1 MPU Registers
SPRU749A
-
An interrupt request from MPU interrupt handler. The MPU interrupt
handler sets the nIRQ_SET signal to logic low and initiates the restarting
of the ARM_CK, ARM_INTH_CK, Rhea_CK, DMA_CK, and TC_CK
clocks. Depending on the setting of the ARM_IDLECT1/2 registers,
peripherals clocks can also restart. This is a valid wake-up condition for
MPU, TC, and DPLL.
-
An interrupt request from the DSP level2 interrupt handler. This initiates
the restarting of the DSP_CK, DSP_INTH_CK, and TC_CK clocks.
Depending on the setting of the ARM_IDLECT1/2 registers, peripheral
clocks can also restart. This signal must remain active until the DSP
asserts the DSP_IDLE signal low. This is a valid wake-up condition for
DSP, TC, and DPLL.
-
L3_OCPI_EN pin: When the L3_OCPI_EN pin is pulled high, the TC_CK,
TC1_CK, and TC2_CK, and the L3_OCPI_CK restart and the TC_CK,
L3_OCPI_CK, TC1_CK, and TC2_CK keep running as long as the pin
remains asserted high. This is a valid wake-up condition for TC and DPLL
only.
-
TCLB_DMAREQ: When the system DMA controller receives an
asynchronous request from the traffic controller, this signal is set high to
enable the DMA_CK/TC_CK and DMA_CK/TC_CK to keep running as
long as the DMA operates. This is a valid wake-up condition for TC and
DPLL only.
-
Rhea_DMAREQ: When the system DMA controller receives a request
from the TIPB-bridge, this signal is asserted high to enable the
TC_CK/Rhea_CK/DMA_CK and the TC_CK/Rhea_CK/DMA_CK to keep
running as long as the DMA operates. This is a valid wake-up condition
for TC and DPLL only.
All registers are 32-bit registers. MPU clock generation and system reset
control registers are accessed by the MPU only. DSP control registers are
accessed by the DSP and the MPU through the MPU interface.
The MPU registers are listed in Table 62. Table 63 through Table 72 provide
register bit descriptions.
Clock Generation and Reset Management
OMAP3.2 Subsystem 141