Texas Instruments OMAP5912 Reference Manual page 792

DSP DMA
Table 115. Channel Status Registers (DMA_CSR0...DMA_CSR5) (Continued)
Bit Name
5 BLOCK
4 LAST
3 FRAME
2 HALF
168 Direct Memory Access (DMA) Support
Function
Whole block status bit. The DMA controller sets
BLOCK only if BLOCK_IE=1 in the DMA_CICR
and all of the current block has been transferred
from the source port to the destination port.
0: Current block transfer has not finished yet.
1: The whole block has been transferred. A
channel interrupt has been sent to the DSP CPU
(another one may have started, if
DMA_CCR2.AUTOINIT = 1).
Last frame status bit. The DMA controller sets
LAST only if LAST_IE = 1 in the DMA_CICR and
the DMA controller has started transferring the last
frame from the source port to the destination port.
0: Last frame has not started yet.
1: The DMA has started transferring the last frame.
A channel interrupt has been sent to the DSP
CPU.
Whole frame status bit. The DMA controller sets
FRAME only if FRAME_IE = 1 in DMA_CICR and
the current frame has been transferred from the
source port to the destination port.
0: Transfer of the current frame is still in progress.
1: A complete frame has been transferred. A
channel interrupt has been sent to the DSP CPU.
Half frame status bit. The DMA controller sets
HALF only if HALF_IE = 1 in DMA_CICR and the
first half of the current frame has been transferred
from the source port to the destination port:
0: First half of the current frame has not finished
transferring yet.
1: First half of the current frame has been
transferred. A channel interrupt request has been
sent to the DSP CPU.
Type Reset
R 0
R 0
R 0
R 0
SPRU755B