Texas Instruments OMAP5912 Reference Manual page 415

OMAP5912 Clock Architecture
Table 16. Control for Special Components
Components
32-kHz oscillator
12-MHz oscillator
LDO
DPLL
APLL
Table 17. Mode Description
Modes Power Dissipation
Deep sleep Lowest
Big sleep Caused by gates clocked by 32-kHz
clocks and clocks derived from 96-MHz
PLL
Awake Nominal
60 Clocks
Software Control
OSC32K_PWRDN_R
CONF_OSC1_PWRDN_R
CONF_LDO_PWRDN_CNTRL_R
SOFT_LDO_SLEEP
PLL_ENABLE
None
Table 17 details the OMAP5912 sleep modes as they relate to power
dissipation and clocks.
Notes
Control in RTC register file
Control in OMAP5912 configuration register
file
Dedicated embedded LDO for DPLL control in
OMAP5912 configuration register file
Control in ULPD register file
Converts 12-MHz to19.2-MHz clock input to
high-frequency clock used in OMAP3.2 clock
tree
Control in DPLL register file
Converts 12-MHz to 19.2-MHz clock to
48-MHz clock
APLL active whenever a request for 48-MHz
clock is set to 1.
Clocks
32 kHz for wake-up detection
Each active clock (32-kHz clocks and
clocks from 96-MHz PLL) can be gated.
32-kHz clocks and system clocks
SPRU751A