Texas Instruments OMAP5912 Reference Manual page 943

Multimedia processor device overview and architecture

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Interrupt Interface

An Example of DSP Interrupt Handling

Interrupt Sequence

The DSP interrupt interface augments DSP interrupt handler capability by

enabling you to define edge-triggered or level-sensitive implementations for

each of external interrupt lines. The DSP interrupt interface allows you to

program the edge- or level-sensitivity of the two level 1 interrupts where IRQ

and FIQ are routed.

Figure 14−1 shows an example of interrupt handling.

Table 31 shows the DSP interrupt sequence for an IRQ interrupt only. The FIQ

interrupt sequence is identical.

Interrupt Sequence

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