Texas Instruments OMAP5912 Reference Manual page 314

Multimedia processor device overview and architecture

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CPU priority bit

When CPU_PRIORITY = 1, the DSP subsystem CPU, MPUI, and DMA

have the following priority in arbitration of TIPB bridge accesses:

If CPU_PRIORITY = 0, the CPU, MPUI, and DMA accesses to the TIPB

bridge are arbitrated in rotating priority fashion.

Wait state bits for strobe 0 and strobe 1

The strobe 0 field sets the access rate for the following peripherals:

TIPB registers

CLKM2 registers

DSP interrupt handler 2.0

DSP interrupt handler 2.1

The strobe 1 field sets the access rate for the following peripherals:

UART3 (test)

McBSP1 (audio PCM)

McBSP3 (optical)

DSP MPUI register

OMAP5912 TIPB switch

GP timer (x8)

32-kHz synchronization timer

The control mode register bits [5−3] and [8−6] contain the number of wait

states required to generate the appropriate strobe frequency (see Table 14).

DSP Subsystem

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