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3.2.3
DMA LCD Channel Sharing Feature
SPRU755B
A(n+1) = A(n) + ES_B1 + (FI_B1 – 1)
where FI_B1 = ((Stride_FI_B1 – 1) * ES_B1) + 1
When A(n) reaches BB1, A(n+1) = TB2: block 2 becomes active.
When block 2 is active:
A(0) = TB2A.
A(n+1) = A(n) + ES_B2 + (EI_B2 – 1)
where EI_B2 = ((Stride_EI_B2 – 1) * ES_B2) + 1
A(n) is incremented in this way until the end of the current frame, that is: as
long as Element_counter_B2 ≠ 0.
When end of frame (but not end of block 2) is reached, that is:
Element_counter_B2 = 0 and Frame_counter_B2 ≠ 0:
A(n+1) = A(n) + ES_B2 + (FI_B2 – 1)
where FI_B2 = ((Stride_FI_B2 – 1) * ES_B2) + 1
When A(n) reaches BB2, A(n+1) = TB1: block 1 becomes active again.
Note:
Both Stride_EI_B1/2= 1 (equivalent to EI_B1/2 = 1) and Stride_FI_B1/2 = 1
(equivalent to EI_B1/2 = 1) give consecutive element accesses, hence the
same behavior as with the post-incremented addressing mode.
In dual-block mode, block 2 can be active first.
The LCD channel in the OMAP 3.2 system DMA supports the LCD controller.
The
lcd_destination_port
(DMA_LCD_CTRL) sets the DMA to use the LCD controller. The OMAP LCD
controller supports 16-bit single accesses. See the Multimedia Processor
Display Interface Reference Guide (SPRU764) for detailed information about
the LCD controller.
LCh-D is enabled differently depending on which LCD controller used:
In OMAP LCD controller mode, the LCD channel is enabled when the
-
OMAP LCD controller is enabled; that is, when bit LCDEN = 1 in the LCD
control register (LCDCONTROL). For more information, see the LCD
control register description in the Multimedia Processor Display Interface
Reference Guide (SPRU764).
bit
in
the
DMA
Direct Memory Access (DMA) Support
System DMA
LCD
control
register
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