Texas Instruments OMAP5912 Reference Manual page 439

Reset Architecture
Table 5. Reset Sources for Peripherals (Continued)
Peripheral Name
MPU level 2 interrupt
handler
MMC/SDIO1
32-kHz watchdog
SHA-1/MD5
DES/3DES
FAC
OS Timer ||
MPUIO ||
†
OCP SWRST: Reset software done in corresponding module.
‡
SWRST1: PER_EN (bit 0) in ARM_RSTC2 is cleared to 0.
§
SWRST2: Set ARM_RST (bit 0) in ARM_RSTCT1 and clear DSP_EN (bit 1) in ARM_RSTCT1.
¶
SWRST3: DSP_PEREN (bit 0) in DSP_RSTCT2 is cleared to 0.
#
Warm reset: Source can be MPU_RST, global software reset, or 32-kHz watchdog time-out.
||
SW control via RESET_CONTROL register (see Table 51).
k
SW control via MOD_CONF_CTRL_1[23].
22 Initialization
HW Reset
Class 2 Modules (Continued)
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1/ 32-kHz
WD
SW Reset Wrapper/
Switch
OCP SWRST OCP wrapper
OCP SWRST OCP wrapper
OCP SWRST OCP wrapper
OCP SWRST OCP wrapper
OCP SWRST OCP wrapper
No pvci2rhea
No TIPB
No No
Wrapper/Switch Reset
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
Cold reset/Warm
reset/ARM_WD/SWRS
T2/SWRST1
SPRU752B