Texas Instruments OMAP5912 Reference Manual page 1092

Table 13. Receive Register Bit Description (SPI_RX—0x038)
Bit Name
31:0 SPI_RX
Note: The number of bits of the word to be received is programmed through the NB bit field in SPI_CTRL register. Receive
register (SPI_RX) data read must be completed according to the received word bit length and in the proper sequence
register access.
The SPI_RX register is considered to be empty if the most-significant byte part of the received word has been read (in
functional mode only and not in emulation mode). If the number of bits of the received word is not aligned on a byte
boundary, the unused bits are read as undefined value.
The SPI_RX register is a 32-bit register that is 16-bit, or 32-bit addressable. Partial register reads with successive 16-bit
accesses can be used to read the receive register. In this case, the LSB must be read before the MSB part of the received
word.
Table 14. Test Register Bit Description (SPI_TEST—0x03C)
Bit Name
31:11 Reserved
10:6 RTSPEN
5 RCV
4 WCV
3 RTV
2 WTV
1 FDO
0 TMODE
SPRU760B
Base Address = 0xFFFB 0C00, Offset = 0x38
Function
Receive data
Base Address = 0xFFFB 0C00, Offset = 0x3C
Function
A read access returns 0.
Read value of TSPEN
Read clock value
Write clock value
Read test value (spy TSPDI)
Write test value (force TSPDO)
Force TSPDO to read value from WTV bit: Active
high
Test mode enable: Active high
When the test mode is selected by setting the TMODE configuration bit in the
SPI_TEST register, it enables the following features:
TSPDO is fed back to TSPDI.
-
It is possible to control and monitor the TSPDO, TSPDI, and CLK_S pins.
-
When the test mode is not active, a read to the SPI_TEST register always
returns 0.
SPI Master/Slave
Access Reset
R 0x00000000
Access Reset
R 0x000000
R 0
R 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
Serial Interfaces 27