Dsp Memory - Texas Instruments OMAP5912 Reference Manual

DSP Memory

3 DSP Memory
22 DSP Subsystem
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TMS320C5510 DSP Functional Overview (SPRU312) (only CPU sections
apply to the OMAP5912 device)
The DSP subsystem contains four types of tightly coupled memory to provide
maximum efficiency of the DSP CPU.
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Dual-access RAM (DARAM)
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Single-access RAM (SARAM)
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Programmable dynamic ROM (PDROM)
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Configurable I-cache structure
The CPU uses six sets of buses to simultaneously fetch up to 32 bits of
program and to read up to 48 bits of data operands from memory (or write up
to 32 bits to memory). To achieve maximum performance from the
architecture, the programmer must pay close attention to placement of code
and data structures within the on-chip memory resources. For more details,
see TMS320C55x DSP Programmers Guide (SPRU376).
Loosely coupled memory devices can be accessed via the traffic controller
module. This flexible memory interface permits DSP access to another block
of SRAM (shared with the MPU) as well as external memory devices such as
flash memory and SDRAM.
Figure 4 shows DSP memory connections.
SPRU750A