Texas Instruments OMAP5912 Reference Manual page 987

Layer 4 Interconnect
Table 10. MPU Peripherals Connected to the MPU Shared TIPB Bridge Instantiation
OMAP 5912
Peripheral
Interface
HDQ/1-Wire TIPB
µWIRE
TIPB
MMCSD/IO1 Wrapper
OCP
MPUIO TIPB
2 x LPG TIPB
SoSSI Wrapper
VIA
RTC TIPB
Memory Stick TIPB
PWL TIPB
PWT TIPB
FAC TIPB
OS timer TIPB
USBOTG Wrapper
OCP
† Address bus alignment:
Byte: The least significant bit of the peripheral address bus corresponds to a byte address in the peripheral.
16-bit: The least significant bit of the peripheral address bus corresponds to a 16-bit address in the peripheral.
32-bit: The least significant bit of the peripheral address bus corresponds to a 32-bit address in the peripheral.
36 Peripheral Interconnects
Instantiation
Address Bus Address Bus
{
Alignment
Data
Byte 8
Byte 16
16b 16
16b 16
Byte 8
32b 32
Byte 8
32b 32
Byte 8
Byte 8
Byte 16
Byte 32
Byte 16
TIPB Router
Access Size Access Size
8b 16b 32b
R − − Shared MPU
− R − Shared MPU
− R − Shared MPU
− R − Shared MPU
R − − Shared MPU
− − R Shared MPU
R − − Shared MPU
− − R Shared MPU
R − − Shared MPU
R − − Shared MPU
− R − Shared MPU
− R R Shared MPU
− R − Shared MPU
SPRU758A