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Memory Interfaces for the EMIFS
Figure 18.
Single-Page Program DMA in Postwrite Mode
Software programs the address.
Software programs the program command.
Software programs the NND_FIFOCTRL register
(FIFO_SIZE and BLOCK_COUNTER field).
Software enables events if needed.
Software enables DMA in system DMA.
Software enables postwrite.
N.F.C writes the data to N.M.F.C and empties the
FIFO.
When FIFO is empty, Fldmareqn is asserted low.
(n)
DMA writes the data in the FIFO.
When FIFO is full, counter is decremented.
Fldmareqn is asserted high.
2.1.18
NAND Flash Memory Core Support
Table 12. Characteristics of Supported NFMCs
1Gb/
128 MB
Number of
262144
pages
Page size+
512+16
spare (bytes)
Number of
8192
blocks
50
Memory Interfaces
(n)
(n)
(n)
Table 12 summarizes the characteristics of supported NFMCs.
512Mb/
64 MB
131072
512+16
4096
Host sends "end
program" command.
(n)
(n)
Last write as counter = 0.
256Mb/
128Mb/
32 MB
16 MB
65536
32768
512+16
512+16
2048
1024
Host can check the
status of program
operation.
Ready/busy_
Fldmareqn
(DMA request)
Note: ECC not
represented.
64Mb/
32Mb/
8 MB
4 MB
16384
8192
512+16
512+16
1024
512
SPRU756A
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