Texas Instruments OMAP5912 Reference Manual page 1019

32-Bit Watchdog Timer General Overview
Table 7. Watchdog System Configuration Register (WD_SYSCONFIG)
Bit Name
31:6 RESERVED
5 EMUFREE
4:2 RESERVED
1 SOFTRESET
0 AUTOIDLE
Table 8. Watchdog System Status Register (WD_SYSSTATUS)
Bit Name
31:8 RESERVED
7:1 RESERVED
0 RESETDONE
16 Timers
Base Address = 0xFFFE B000, Offset = 0x10
Function
Write 0s for future compatibility
Read returns 0
Enable sensitivity to suspend signal (emulation)
0: The module freezes its internal logic upon
suspend assertion.
1: The module ignores the suspend input.
Write 0s for future compatibility
Read returns 0
Software reset. Set this bit to 1 to trigger a module
reset. This bit is automatically reset by hardware.
During read, it always returns 0.
0: Normal mode
1: The module is reset.
Internal OCP gating strategy
0: Interface clock is free-running.
1: Interface clock gating is active.
Base Address = 0xFFFE B000, Offset = 0x14
Function
Reserved
Reserved
Internal reset monitoring
0: Internal module reset is ongoing.
1: Reset completed
This register provides system status information about the module.
R/W Reset
R/W 0x0000000
R/W 0
R/W 0x0
R/W 0
R/W 0
R/W Reset
R 0x0000000
R 0x00
R 0
SPRU759B