Texas Instruments OMAP5912 Reference Manual page 381

OMAP3.2 DPLL
26 Clocks
For PLL_MULT = 0 or 1, the clkout is not synthesized. Hence, the output -clock
duty cycle (clkout) is directly dependent on the input-clock duty cycle (clkref).
The lock times depend on the values of PLL_MULT and PLL_DIV and the
clkout frequency as given below :
Lock time in number of clkref cycles:
# clkref clocks=4N(11D+28)
where D=1+log (N/(fin*M*xmin)) rounded up to the nearest positive inte-
2
ger (7 max), and fin is the input clock frequency.
The value of xmin in the equation for D is dependent on technology. It must be
set to the delay of A with 10 stages in the delay chain measured in min delay
conditions.
-
1.5 V xmin = 5.6 ns
Example:
-
1.5 V
-
CKref = 10 MHz
-
N = 1
-
M = 2
D = 1+log (1/(2*10E6*5.6E-9)) = 1+log
2
up)
Number of clkref clocks = 4(11(5)+28) = 332
Time = (332)(100 nsec) = 33.2 µsec
Each time the DPLL control register is written to, the mode in which the DPLL
operates changes automatically. If the DPLL is operating in the synthesizer
mode, it switches automatically to the bypass mode. Depending on the new
control register content, the DPLL either initiates a new lock sequence or
remains in the bypass mode (see Figure 5).
(8.93) = 4.158 = 5 (rounded
2
SPRU751A