Texas Instruments OMAP5912 Reference Manual page 293

DSP Memory
Table 3. Global Control Register (GCR) (Continued)
Bit Name
11 Global Flush
½ ramset Presence
10
9 Way Presence
½ ramset Number
8:5
4:3 Way Number
2 Streaming
1 Ram Fill Mode
0 Global Enable
30 DSP Subsystem
Description
Global flush configuration:
0: The flush configuration must take into account the specific flush
bits (n-way and ½ ramset).
1: All the I-cache is flushed when CACLR = 1.
(Line valid bits are invalidated and ramset tag valid bit is
invalidated.)
½ ramset presence:
0: No ½ ramset
1: N x ½ ramset
Way presence:
0: No way
1: N-way (set-associative or direct-mapped)
I-cache ½ ramset number:
1..2 ½ ramset number(1 is coded by 0000/b and 2 otherwise)
I-cache way number:
x0: 1-way (direct-mapped)
x1: 2-way (set-associative)
Streaming enable
1: Streaming enabled
This is the only supported configuration.
Type of load for a ramset flush line
1: RAM fill mode (fill all lines of set )
(Invalidation of the TAG valid bit during fill/ after fill is complete; TAG
valid bit is set).
This is the only supported configuration.
Global enable configuration:
0: Takes into account the specific enable bits (n-way and ½ ramset)
1: All I-cache enabled when CAEN=1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPRU750A