Texas Instruments OMAP5912 Reference Manual page 877

2.2.1 NAND Flash Software Controller Overview
2.2.2 EMIFS Interface With NAND CE Care Flash Device Option
SPRU756A
The features of the system are as follows:
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The NAND flash device is mapped on one of the chip-selects of the EMIFS
interface of the OMAP5912 device.
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One 8-bit- or 16-bit-wide interface NAND flash device is supported on
EMIFS. Either the MPU or DSP (hereafter called the processor) can
access and control the NAND flash device.
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The processor manages the command sequence required for block
erase, write, read, and block invalidation and management. To reduce
processor overhead, either the system DMA (GDMA) or the DSP DMA can
be used to write or read blocks of data to/from the NAND flash device.
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There are two options for ECC calculation:
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The MPU or DSP calculates the ECC by software.To reduce
processor overhead, the NAND flash controller peripheral module can
calculate the ECC with the support of the DMA for moving the data.
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Using the NAND flash controller peripheral, an ECC can be calculated
on up to nine blocks of 256 bytes at one time before it is required to
read the ECC calculation results.Section 2.2.3 explains the write
sequence example that is required to use a NAND flash device with
the OMAP5912.
Some NAND flash devices require that CS be low during the read access time
(tR); hereafter, these devices are called NAND CE Care. Thus, a standard
OMAP5912 chip-select cannot be used for the NAND flash chip-select.
However, some NAND flash devices do not require that CS be low during tR;
these devices are called NAND CE Don't Care. The OMAP5912 chip-select
can be used directly for them.
The interface of a NAND CE Care flash device to the OMAP5912 is possible
by using FLASH.CS2UOE (output enable) and FLASH.CS2UWE (write
enable). The only exception to this policy is that several signals that are used
for the NAND flash interface are muxed on signals that are needed for support
of synchronous burst flash memories.
If both NAND and synchronous burst flash memories are required in the
system, two solutions are available:
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Generate the NAND flash interface signals by GPIOs at some loss of
system performance
Software NAND Flash Controller
Memory Interfaces 71