Texas Instruments OMAP5912 Reference Manual page 160

Multimedia processor device overview and architecture
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Table 24. EMIFS Dynamic Wait States Control Register (EMIFS_DWS)
Bit
Field
31:8
Reserved
7
Full handshake enable
for CS3
6
Full handshake enable
for CS2
5
Full handshake enable
for CS1
4
Full handshake enable
for CS0
3
Dynamic wait states
enable for CS3
2
Dynamic wait states
enable for CS2
1
Dynamic wait states
enable for CS1
0
Dynamic wait states
enable for CS0
102
OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0x40
Description
Reserved
Enables Full-/non-full-handshaking mode for
CS3
0: Full-handshaking
1: Non-full-handshaking
Enables Full-/non-full-handshaking mode for
CS2
0: Full-handshaking
1: Non-full-handshaking
Enables Full-/non-full-handshaking mode for
CS1
0: Full-handshaking
1: Non-full-handshaking
Enables Full-/non-full-handshaking mode for
CS0
0: Full-handshaking
1: Non-full-handshaking
Enables dynamic wait states mode for CS3
0: Dynamic wait states mode disabled
1: Dynamic wait states mode enabled
Enables dynamic wait states mode for CS2
0: Dynamic wait states mode disabled
1: Dynamic wait states mode enabled
Enables dynamic wait states mode for CS1
0: Dynamic wait states mode disabled
1: Dynamic wait states mode enabled
Enables dynamic wait states mode for CS0
0: Dynamic wait states mode disabled
1: Dynamic wait states mode enabled
This register controls if EMIFS has dynamic wait states by using the ready
signal.
R/W
Reset
R/W
0x000000
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SPRU749A

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