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SPRU755B
All elements must be transferred continuously within a frame. That means
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that it cannot be synchronized on element boundary, and if
single/dual-indexed addressing mode is used, element index (EI) must be
set to 1.
No packing or bursting can be done over frame boundary. It does not help
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to set frame index FI_ to 1.
No packing or bursting can be done over block boundary.
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Once the type of access is decided, the current byte address can be
incremented by 1, 2, 4, or 16 to reach the next memory space location. Then,
the DMA port checks its physical channel FIFO to see if there is enough data
(write access) or enough space (read access) in the FIFO, before issuing the
access.
It is assumed that:
A 16-bit target memory or peripheral also has a byte-write/read capability.
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A 32-bit target memory or peripheral also has a byte and word16
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write/read capability.
If this is not the case, then the software must carefully set up the transfer as
follows:
Follow the address alignment rules in Section 4.12, Data Alignment.
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Set the data_type to the same size as the peripheral register width that is
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the source or the destination of the DMA transfer.
These rules apply only when the constant address mode is used (which
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is likely to be the case when a single register in source/destination), and
no packing can be enabled.
Packing is controlled by the source and destination packing bits and packs
several elements into a larger access element (word16 or word32). For
instance, if the data_type is set to s16, the source port supports 32-bit
accesses, the source packing is enabled, and the address is aligned on
word32, then the source port makes two 16-bit accesses and packs them to
a word32 before sending word32 to the destination port. If the source port uses
the constant addressing mode and the packing bit is enabled, then the packing
bit is ignored.
Direct Memory Access (DMA) Support
System DMA
53
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