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Figure 12.
LCD One-Block Mode Transfer Scheme
SPRU755B
Step 1: Registers are set as:
DMA_LCD_CTRL
BLOCK_MODE = 0 (one block)
BLOCK_IT_IE = 1
BUS_ERROR_IT_IE = 1
LCD_SOURCE_PORT = 0 (SDRAM)
DMA_LCD_TOP_B1_U = 0x000B
DMA_LCD_TOP_B1_L = 0x0000
DMA_LCD_BOT_B1_U = 0x000B
DMA_LCD_BOT_B1_L = 0x00DE
DMA_LCD_TOP_B2_U = irrelevant
DMA_LCD_TOP_B2_L = irrelevant
DMA_LCD_BOT_B2_U = irrelevant
DMA_LCD_BOT_B2_L = irrelevant
Step 2: The transfer starts when the enable (hardware) signal from the
OMAP LCD controller is asserted high.
The transfer runs, and an interrupt is generated at the end of the
block.
SDRAM
0x0B 0000
Video block
0x0B 00DE
Step 3: When an interrupt occurs, read the DMA_LCD_CTRL register, to
know the source of the interrupt.
If DMA_LCD_CTRL[3] = 1 (that is to say, block_1_it_cond = 1), end
of block 1 interrupt is detected.
If end of block is reached, the DMA restarts at the top of the block.
Step 4: Reset DMA_LCD_CTRL [3] and wait for another interrupt.
LCD_TOP_BLOCK_1
DMA
LCD_BOT_BLOCK_1
Direct Memory Access (DMA) Support
System DMA
LCD
controller
77
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