Texas Instruments OMAP5912 Reference Manual page 790

DSP DMA
Table 114. Channel Interrupt Control Registers (DMA_CICR0...DMA_CICR5)
(Continued)
Bit Name
4 LAST_IE
3 FRAME_IE
2 HALF_IE
1 DROP_IE
0 TOUT_IE
166 Direct Memory Access (DMA) Support
Function
Last frame interrupt enable. LAST_IE determines
how the DMA controller responds when it starts
transferring the last frame from the source port to
the destination port.
0: Do not record the last frame event.
1: Set the last bit in DMA_CSR and send channel
interrupt request to the DSP CPU.
Whole frame interrupt enable. FRAME_IE
determines how the DMA controller responds
when the first half of the current frame has been
transferred from the source port to the destination
port.
0: Do not record the frame complete event.
1: Set the frame bit in DMA_CSR and send
channel interrupt request to the DSP.
Half frame interrupt enable. Determines how the
DMA controller responds when the first half of the
current frame has been transferred from the
source port to the destination port:
0: Do not record the half frame event.
1: Set the half bit in DMA_CSR and send the
channel interrupt request to the DSP CPU.
Synchronization event drop interrupt enable
If two DMA synchronization event occurs again
before the DMA controller is done servicing the
previous DMA request, an error has occurred (a
synchronization event drop). DROP_IE determines
how the DMA controller responds when a
synchronization event drop occurs in the channel:
0: Do not record the event drop.
1: Set the drop bit in DMA_CSR and send the
channel interrupt request to the DSP CPU.
Time-out interrupt enable. Determines how the
DMA controller responds to a time-out error at the
source port or the destination port of the channel.
0: Do not record the the time-out error.
1: Set the time-out bit in DMA_CSR and send the
bus error interrupt request to the DSP CPU.
Type Reset
RW 0
RW 0
RW 0
RW 1
RW 1
SPRU755B