Texas Instruments OMAP5912 Reference Manual page 258

TIPB Bridge
Table 119. TIPB Allocation Control Register (RHEA_BUS_ALLOC) (Continued)
Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x04
Bit Name
4 FIXNROUND_PRIORITY
3 PRIORITY_ENABLE
2:0 RHEA_PRIORITY
Table 120. MPU TIPB Control Register (ARM_RHEA_CNTL)
Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x08
Bit Name
15:2 Reserved
1 W_BUF_EN_1
0 W_BUF_EN_0
200 OMAP3.2 Subsystem
Function
Type of priority scheme used in DMA and OCP-I
arbitration:
0: Round-robin scheme used
1: Fixed priority scheme used
0: TIPB bus allocation is done using the
RHEA_PRIORITY bits.
1: MPU has the same priority as the DMA/OCP-I
transfers regarding TIPB bus allocation when it is in
exception mode (IRQ and FIQ).
Defines TIPB priority between MPU and DMA/OCP-I.
000: MPU has priority over the DMA/OCP-I.
001 through 111: DMA/OCP-I has priority over the
MPU, and can perform the programmed number of
accesses before the MPU can access the bus.
Function
0: Posted write buffer is bypassed.
1: Posted write buffer is enabled for MPU public and private
TIPB peripherals having address space assigned to TIPB
strobe 1.
0: Posted write buffer is bypassed.
1: Posted write buffer is enabled for MPU public and private
TIPB peripherals that have address space assigned to TIPB
strobe 0.
R/W Reset
R/W 0
R/W 1
R/W 001
R/W Reset
R/W 0x0000
R/W 0
R/W 0
SPRU749A