Texas Instruments OMAP5912 Reference Manual page 243

Table 98. DSP Boot Configuration Register (DSP_BOOT_CONFIG) (Continued)
Bit Name
9:4 BOOT_RHEA_PTR1
3:0 DSP_BOOT_MODE
Table 99. MPUI Port RAM Configuration Register (DSP_MPUI_CONFIG)
Bit Name
31:16 Reserved
15:0 API_SIZE
Table 100. DSP Miscellaneous (DSP_MISC)
Bit Name
31:9 Reserved
8 CPUBION
7:0 Reserved
Table 101. MPUI Enhanced Control Register (MPUI_ENHANCED_CTRL)
Bit Name
31:1 Reserved
0 DPS_EN
SPRU749A
Base Address = 0xFFFE C900, Offset = 0x18
Function
User-defined pointer that can be used for
application-specific boot code location
DSP boot mode inputs.
Base Address = 0xFFFE C900, Offset = 0x1C
Function
Grants the MPUI exclusive access to the specified
portion of DSP SARAM in HOM. For details on
SARAM configuration, see Table 102
Table 100 describes the DSP miscellaneous register bits. For debug
purposes, this register stores the state of the BION signal (internal to the DSP
subsystem). State is captured at each MPUI clock cycle.
Base Address = 0xFFFE C900, Offset = 0x20
Function
Reflects level of BION signal to DSP subsystem
Base Address = 0xFFFE C900, Offset = 0x24
Function
When 1, dynamic power saving (DPS) mode is
enabled.
Otherwise, DPS is disabled.
When DPS is enabled, the MPUI clock is turned off
when there is no active request from the
MCU/DMA/OCPI.
MPU and MPUI Port
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
000000
0000
Reset
0x0000
0xFFFF
Reset
0x0000
0
0x00
Reset
0x0000
0
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