Texas Instruments OMAP5912 Reference Manual page 1086

Table 4. System Configuration Register Bit Description
Bit Name
31:5 Reserved
4:3 IDLEMODE
2 EN
AWAKEUP
1 SOFTRESET Software reset. Set this bit to 1 to trigger an SPI
0 AUTOIDLE
Table 5. System Status Register Bit Description (SPI_SSR—0x014)
Bit Name
31:1 Reserved
0 RESETDONE Internal reset monitoring
Note: Before accessing or using the module the local host must ensure that internal reset is released by reading the system
status register (SPI_SSR).
SPRU760B
Base Address = 0xFFFB 0C00, Offset = 0x10
Function
A read access returns 0.
Power management, req/ack control
00: Force-idle. An idle request is acknowledged
unconditionally.
01: No idle. An idle request is never acknowledged.
10: Smart idle. An idle request is acknowledged
based on the internal activity of the module.
11: Reserved: Do not use.
Wake-up feature control
0: Wake-up is disabled.
1: Wake-up capability is enabled.
reset. This bit is automatically reset by hardware.
Writing a 0 has no effect.
During reads, it always returns 0.
0: Normal mode.
1: The module is reset.
Internal OCP clock gating strategy
0: OCP clock is free-running.
1: Automatic OCP clock gating strategy is applied,
based on the OCP interface activity.
This register allows control of the OCP interface parameters.
This register provides status information about the reset.
Base Address = 0xFFFB 0C00, Offset = 0x14
Function
A read access returns 0.
0: Internal module reset is ongoing.
1: Reset completed.
SPI Master/Slave
(SPI_SCR—0x010)
Access
R
R/W
R/W
R/W
R/W
Access
R
R
Serial Interfaces
Reset
0x0000000
00
0
0
0
Reset
0x00000000
0
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