Texas Instruments OMAP5912 Reference Manual page 159

Table 20. EMIFS Chip-Select Configuration Register RDMODE Field Definition
Table 21. EMIFS Time-Out Register 1 (EMIFS_PTOR1)
Bit Field
31:8 RESERVED
7:0 DMA
Table 22. EMIFS Time-Out Register 2 (EMIFS_PTOR2)
Bit Field
31:8 RESERVED
7:0 DSP
Table 23. EMIFS Time-Out Register 3 (EMIFS_PTOR3)
Bit Field
31:8 RESERVED
7:0 OCPI
SPRU749A
RDMODE Memory
000 Mode 0: Asynchronous read
001 Mode 1: Page mode ROM read—4 words per page
010 Mode 2: Page mode ROM read—8 words per page
011 Mode 3: Page mode ROM read—16 words per page
100 Mode 4: Synchronous burst read mode
101 Mode 5: Synchronous burst read mode
110 Reserved for future extension
111 Mode 7: Synchronous burst read mode
Base Address = 0xFFFE CC00, Offset = 0x28
Description
Reserved
Number of TC_CK cycles
Base Address = 0xFFFE CC00, Offset = 0x2C
Description
Reserved
Number of TC_CK cycles
Base Address = 0xFFFE CC00, Offset = 0x30
Description
Reserved
Number of TC_CK cycles
Time-out registers 1−3 are used to control the number of TC clock cycles
before DSP, DMA, or OCP requests are made high priority in the dynamic
priority scheme used inside TC.
Traffic Controller
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 0
R/W 0
OMAP3.2 Subsystem 101