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System DMA
Post-Incremented Addressing Mode
70
Direct Memory Access (DMA) Support
Element_counter_B2: Counter that is (re)initiated with the number of ele-
ments per frame inside block 2. Decreased by one at each element trans-
ferred. Initial value EN_B2 is configured in register DMA channel element
number, DMA_CEN.
Frame_counter_B1: Counter that is (re)initiated with the number of
frames inside block 1. Decreased by one at each frame transferred. Initial
value FN_B1 is configured in register DMA channel frame number,
DMA_CFN.
Frame_counter_B2: Counter that is (re)initiated with the number of
frames inside block 2. Decreased by one at each frame transferred. Initial
value FN_B2 is configured in register DMA channel frame number,
DMA_CFN.
EI_B1: Block 1 element index in bytes - 32768 ≤ EI_B1 ≤ 32767.
EI_B2: Block 2 element index in bytes - 32768 ≤ EI_B1 ≤ 32767.
Stride_EI_B1: Number of elements between the beginning of the current
element (n) and the beginning of the next one (n+1) in block 1.
Stride_EI_B2: Number of elements between the beginning of the current
element (n) and the beginning of the next one (n+1) in block 2.
Stride_FI_B1: Number of elements between the beginning of the last ele-
ment of the current frame and the beginning of the first element of the next
frame in block 1.
Stride_FI_B2: Number of elements between the beginning of the last ele-
ment of the current frame and the beginning of the first element of the next
frame in block 2.
FI_B1: block 1 frame index in bytes:
-2147483648 < FI_B1 < 2147483647.
FI_B2: block 2 frame index in bytes:
-2147483648 < FI_B2 < 2147483647.
Address is post-incremented by element size (ES_B1 or ES_B2 depend-
ing on which block is active if in dual-block mode).
DBM = 0 (one block mode)
Only block 1 is active:
A(0) = TB1.
A(n+1) = A(n) + ES_B1 until the end of block 1.
Then, when A(n) reaches BB1, A(n+1) = TB1 again
DBM = 1 (dual block mode)
SPRU755B
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