Texas Instruments OMAP5912 Reference Manual page 339

DSP Memory Management Unit
Table 19. DSP MMU Registers
76 DSP Subsystem
Name
PREFETCH_REG
WALKING_ST_REG
CNTL_REG
FAULT_AD_H_REG
FAULT_AD_L_REG
FAULT_ST_REG
IT_ACK_REG
TTB_H_REG
TTB_L_REG
LOCK_REG
LD_TLB_REG
CAM_H_REG
CAM_L_REG
RAM_H_REG
RAM_L_REG
GFLUSH_REG
FLUSH_ENTRY_REG
READ_CAM_H_REG
READ_CAM_L_REG
READ_RAM_H_REG
READ_RAM_L_REG
DSPMMU_IDLE_CTRL
Base Address = FFFE D200
Description
Prefetch register
Status
Control
MSB fault address
LSB fault address
Fault status
It acknowledge
MSB TTB
LSB TTB
Lock counter
Load entry in TLB
MSB of CAM entry
LSB of CAM entry
MSB of RAM entry
LSB of RAM entry
Global flush
Flush one
MSB read CAM
LSB read CAM
MSB read RAM
LSB read RAM
Idle control register
R/W Offset
R/W 0x00
R 004
R/W
R
R 010
R 014
W 018
R/W 01C
R/W 020
R/W 024
R/W 028
R/W 02C
R/W 030
R/W 034
R/W 038
R/W 03C
R/W 040
R 044
R 048
R 04C
R 050
R/W 054
SPRU750A