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Step 1: Calculate ECC
SPRU756A
The MPU programs the system DMA as follows:
-
Transfers the data in 8-, 16-, or 32-bit word format from SDRAM into the
NAND flash controller
-
Transfer mode (single mode= > channel stop when current transfer
finishes)
-
The DMA creates an interrupt on completion of the transfer.
-
Transfer start (hardware start => on DMA request)
The processor MPU configures the NAND flash controller peripheral as
follows:
-
Selects
the
number
NND_ECC_SELECT register
-
Selects the type of ECC (256/512 byte blocks) by programming the
NND_CTRL register
-
Enables the read and program operation: ECC logic-enable by
programming bit 0 of the NND_CTRL register
-
Enables the clock in the NND_SYSCFG register bit 0.
-
Sets 1 in NND_PSC_CLK (the module runs full-speed for minimum delay
in the ECC calculation)
-
Configures the NAND flash FIFO access
-
Resets the ECC calculation by writing to NND_RESET
Note:
To optimize the transfer from SDRAM to NAND flash controller, keep the
RDY/BUSY signal of NAND flash controller at 1.
-
The processor initiates a write command to the NAND flash device (in the
NAND flash controller) NND_COMMAND.
-
The NAND flash controller sends a DMA request (FIFO mode).
-
The data is written into the NAND flash controller peripheral by the DMA
to the NAND flash FIFO.
-
ECC is calculated.
Software NAND Flash Controller
of
blocks
to
calculate
Memory Interfaces
ECC
on
(1-9)
73
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