Texas Instruments OMAP5912 Reference Manual page 216

Clock Generation and Reset Management
Table 75. DSP Idle Enable Control Register 1 (DSP_IDLECT1) (Continued)
Bit Name
1 IDLXORP_DSP
0 IDLWDT_DSP
Table 76. DSP Idle Enable Control Register 2 (DSP_IDLECT2)
Bit Name
15:6 RESERVED
5 EN_TIMCK
4 RESERVED
3 RESERVED
2 EN_PERCK
158 OMAP3.2 Subsystem
Base Address = 0xE100 8000 or 0x008000, Offset = 0x04
Function
Selects idle entry mode for external reference
peripheral clock.
0: The DSPXOR_CK clock remains active when DSP
enter the idle mode.
1: The DSPXOR_CK clock is stopped in conjunction
with DSP clock when the idle mode is set.
Selects the idle entry mode for the internal
timer/watchdog connected to DSP TIPB.
0: The clock supplied to timer/watchdog remains
active when DSP enters the idle mode.
1: The timer/watchdog clock is stopped in conjunction
with DSP clock when the idle mode is set.
When the timer/watchdog is configured as watchdog
timer, the clock is never shutdown regardless of the
value of the IDLWDT_DSP bit.
Base Address = 0xE100 8000 or 0x008000, Offset = 0x08
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Enables the internal DSP timer clock (DSPTIM_CK).
0: DSPTIM_CK clock is stopped.
1: DSPTIM_CK clock is active and can be stopped
depending on the IDLTIM_DSP bit of DSP_IDLECT1.
This bit must be set to 0.
This bit must be set to 0.
Enables external peripheral clock (DSPPER_CK).
0: DSPPER_CK clock is stopped.
1: DSPPER_CK clock is active and can be stopped
depending on the IDLPER_DSP bit of
DSP_IDLECT1.
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 0x00
R/W 0
R/W 0
R/W 0
R/W 0
SPRU749A