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1.15.2
Generic Power-up Sequence in Oscillator Mode
SPRU753A
-
The ULPD controls the oscillator and inserts proper setup times at
power-up to ensure that a stable clock is released to the system.
-
In this mode, PWRON_RESET must be released only when the 32-kHz
clock and the supply voltage are stable.
-
If RESET_MODE is at 1, the ULPD starts in external clock mode. In this
case, no setup time delay is inserted at power up.
-
An external chip provides the input clock and ensures that it is stable.
-
In external clock mode the PWRON_RESET must be released only when
the system clock, the 32-kHz clock, and the supply voltage are stable.
Power-up in oscillator mode follows this sequence:
1) PWRON_RESET is released, and the first analog cell is enabled
2) The SETUP_ANALOG_CELL2 counter starts counting in order to account
for
the
power-supply
SETUP_ANALOG_CELL2 is 0, because the power supplies are stable
before
the
deassertion
SETUP_ANALOG_CELL2 counter is to be used during exit of deep sleep
mode while the core power supply is ramping from 1 V.
3) When
SETUP_ANALOG_CELL2
SETUP_ANALOG_CELL3
SETUP_ANALOG_CELL3 is used to account for the stabilization of the
12-MHz oscillator.
4) When SETUP_ANALOG_CELL3 underflows, all the analog cells must be
stable. The input system clock is released internally in ULPD.
5) The ULPD FSM1 transitions to awake mode.
6) The ULPD enables the input clock to OMAP3.2.
Ultralow-Power Device
setup
time.
The
of
the
power-up
underflows,
counter
starts
Power Management
reset
value
of
reset.
The
the
counting.
43
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