Texas Instruments OMAP5912 Reference Manual page 850

Memory Interfaces for the EMIFS
44 Memory Interfaces
the NFC asserts low the interrupt (if event FIFO_EMPTY is unmasked). The
CPU refills the FIFO and clears the interrupt. When the counter reaches zero,
the interrupt is also asserted (if event COUNT_ZERO is unmasked). To finish
programming the NFMC, the command 0x10 must be sent.
-
The host writes the data in the FIFO of the NFC. Once the FIFO is full, all
access is stalled.
-
When the FIFO is full, the event FIFO_FULL is set, the NFC sends the data
from the FIFO to the NFMC, and the internal counter is decremented.
-
When the FIFO is empty, the event FIFO_EMPTY is set, and interrupt is
asserted if unmasked (active low).
-
When the FIFO is empty and the counter is not zero, the host writes a new
batch of data in the FIFO of the NFC.
-
If the counter is zero, the event COUNT_ZERO is set and the interrupt is
asserted if unmasked, the NFC sends the data from the FIFO to the
NFMC, and the postwrite mechanism is stopped.
-
The host clears the pending event(s) by writing to NND_STATUS of the
NFC.
While the FIFO is being filled, access to command, data, and address registers
is stalled.
When postwrite goes from 0 to 1:
-
The FIFO is flushed. (FIFO_EMPTY event is set. Depending on the value
of MSK_EMPTY, the interrupt is asserted or not.)
-
The internal counter is loaded with the BLOCK_COUNT value of the
NND_FIFOCTRL register.
When the postwrite goes from 1 to 0:
-
Postwrite is aborted.
Any write past the last byte of FIFO is discarded. For instance, if the
FIFO_SIZE is 16 and the pointer is on the 14
write of a data equal to X3X2X1X0 is placed on the FIFO :
th
position of the FIFO, a 32-bit
th
13 14
Be = 0 data X0
Be = 1 data X3
th th th
15 16
X1 X2
X2 X1
SPRU756A