32-Bit Watchdog Timer General Overview; Posted And Nonposted Writes - Texas Instruments OMAP5912 Reference Manual

32-Bit Watchdog Timer General Overview

1.1

Posted and Nonposted Writes

Table 1. Watchdog Timer Clock Domains
Device
32-kHz watchdog
†
The MPU peripheral clock is typically at half the frequency of the MPU clock frequency.
Table 2. Write Posted Status Register (WWPS)
Bit Name
4 W_PEND_WSPR
3 W_PEND_WTGR
2 W_PEND_WLDR
1 W_PEND_WCRR
0 W_PEND_WCLR
10 Timers
There are two clock domains in the watchdog: the timer clock and the interface
clock. Table 1 lists these clocks and their frequencies.
Timer Clock
CLK32K_IN: 32 kHz
The counter and its related registers (WCLR, WCRR, WLDR, WTGR and
-
WSPR registers) are clocked by the timer clock.
The read/write interface (designated as the OCP interface) which
-
manages the data flow to and from the MPU is clocked by the interface
clock. Timer registers WDIR, WD_SYSCONFIG, WD_SYSSTATUS and
WWPS are also clocked by the interface clock
For the 32-kHz watchdog timer, any write to a register located in the timer clock
domain is done in posted mode.
In effect, the write is acknowledged after it has been resynchronized to the
32-kHz clock. You can perform concurrent writes to the timer clock domain
registers and verify that they were acknowledged by reading the status bit in
the write posted status register (WWPS). In the case where a register
associated write posted status bit is set, a write from the MPU is not
acknowledged (see Table 2).
Function
When equal to 1, a write is pending to the WSPR register.
When equal to 1, a write is pending to the WTGR register.
When equal to 1, a write is pending to the WLDR register.
When equal to 1, a write is pending to the WCRR register.
When equal to 1, a write is pending to the WCLR register.
Interface Clock
MPU peripheral clock : 96 MHz †
SPRU759B