Texas Instruments OMAP5912 Reference Manual page 250

Mailboxes
Table 110. DSP to MPU Mailbox 2B Register (DSP2MPU2B)
Bit Name
15:0 DSP2MPU2B This register stores the data to be shared for
Table 111. MPU to DSP Mailbox 1 Flag Register (MPU2DSP1_FLAG)
Bit Name
15:1 Reserved
0 INT
Table 112. DSP to MPU Mailbox 1 Flag Register (DSP2MPU1_FLAG)
Bit Name
15:1 Reserved
0 INT
Table 113. DSP to MPU Mailbox 2 Flag Register (DSP2MPU2_FLAG)
Bit Name
15:1 Reserved
0 INT
192 OMAP3.2 Subsystem
Base Address = 0xFFFC F000, Offset = 0x14
Function
the DSP-to-MPU interrupt in mailbox 2. The
DSP2MPU2 interrupt is generated to
MPU/DMA/OCP-I when this register is
written. When this register is read by MPU,
(DSP2MPU2_FLAG) is reset.
Base Address = 0xFFFC F000, Offset = 0x18
Function
0: No interrupt pending
1: Interrupt generated
Base Address = 0xFFFC F000, Offset = 0x1C
Function
0: No interrupt pending
1: Interrupt generated
Base Address = 0xFFFC F000, Offset = 0x20
Function
0: No interrupt pending
1: Interrupt generated
R/W
R/W by DSP
R by MPU/DMA/OCP-I
R/W
R/W
R by MPU/DMA/OCP-I
No access by DSP
R/W
R/W
R by DSP
No access by
MPU/DMA/OCP-I
R/W
R/W
R by DSP
No access by
MPU/DMA/OCP-I
Reset
0x0000
Reset
0x0000
0
Reset
0x0000
0
Reset
0x0000
0
SPRU749A