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Memory Interfaces for the EMIFS
Table 28. NAND Controller Mask Register (NND_MASK)
Bit
Name
31-4
Reserved
3
MSK_EMPTY
2
MSK_FULL
1
MSK_COUNT
0
MSK_READY
60
Memory Interfaces
direct access to ChipEn2 signal, it must be set to low when access is
performed and not set back to high before all operations to the NFMC are
terminated.
Bit 13: The WriteProt2 bit provides inadvertent write/erase protection during
power transitions. The NFMC internal high voltage generator is reset when the
WriteProt2 signal is low. This signal is low during reset, and software must
write a 1 in this location before any access to the NFMC.
Bit 14: The ChipEn3 directly controls the NFMC selection control. When
ChipEn3 is high, access to the NFMC is impossible. When ChipEn3 goes high
during a read operation, the NFMC returns to standby mode. However, when
the NFMC is in a busy state during a program or an erase operation, the NFMC
ignores ChipEn3 and does not return to standby mode. Because software has
direct access to ChipEn3 signal, it must be set to low when access is
performed and not set back to high before all operations to the NFMC are
terminated.
Bit 15: The WriteProt3 bit provides inadvertent write/erase protection during
power transitions. The NFMC internal high voltage generator is reset when the
WriteProt3 signal is low. This signal is low during reset, and software must
write a 1 in this location before any access to the NFMC.
Bit 16: Postwrite bit. Writing 1 to this bit enables the postwrite mechanism.
Access to the internal FIFO is possible. The host or DMA writes data in the
FIFO, and the NFC is responsible for unloading the FIFO to the NFMC.
Bit 17: Prefetch bit. Writing 1 to this bit enables the prefetch mechanism.
Access to the internal FIFO is possible. The NFC fetches data from the NFMC
and fills the FIFO. The host or DMA reads data from the FIFO.
Bits 31-18: Reserved
Description
Reserved
Mask. When 0, event for FIFO empty is masked.
Mask. When 0, event for FIFO full is masked.
Mask. When 0, event for counter reaching zero is masked.
Mask. When 0, event for data ready is masked.
This register masks event sources. At reset, all event sources are masked. To
unmask an event, a 1 must be written in the bit of the event to be unmasked.
SPRU756A
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