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2
2.3
I
C Controller Features
2
2.4
I
C Master/Slave Controller Signal Pads
SPRU760B
The main features of the I
Compliance with Philips I
-
Standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s)
-
support
7-bit and 10-bit device addressing modes
-
General call
-
Start/restart/stop
-
Multimaster transmitter/slave receiver mode
-
Multimaster receiver/slave transmitter mode
-
Combined master transmit/receive and receive/transmit mode
-
Built-in FIFO for buffered read or write
-
Module enable/disable capability
-
Programmable clock generation
-
16-bit wide access to maximize bus throughput
-
Low-power design
-
Two DMA channels
-
Wide-interrupt capability
-
2
The current I
C does not support:
High-speed (HS) mode for transfer up to 3.4M bits/s
-
C-bus-compatibility mode
-
Data are communicated to devices interfacing with the I
line (SDA) and the serial clock line (SCL). These two wires carry information
between the DSP or MPU device and other devices connected to the I
2
The I
C is a shared peripheral that can be allocated to the MCU or the DSP.
Both the SDA and SCL are bidirectional pins. They must be connected to a
positive supply voltage via a pullup resistor. When the bus is free, both pins
are high. The driver of these two pins has an open drain to perform the required
wired-AND function.
2
C controller are:
2
C specification version 2.1, January 2000
I2C Multimaster Peripheral
2
C via the serial data
2
C bus.
Serial Interfaces
57
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