Texas Instruments OMAP5912 Reference Manual page 198

Clock Generation and Reset Management
140 OMAP3.2 Subsystem
(sending a command from the MPU to DSP via the mailbox is one way
to start this sequence). If the DSP has not been enabled after reset, it
is only necessary to clear the ARM_CKCTL(EN_DSPCK) register bit
to 0 in order to reach the idle state for this domain.
J
The MPU must wait until the DSP has reached the idle state.
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Disable the MPU watchdog timer.
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Set the ARM_IDLECT1, ARM_IDLECT2, and ARM_IDLECT3
register bits in preparation for going to idle (MPU, DSP, TC, and DPLL
idle entries are all affected by these registers).
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Configure the EMIFS and EMIFF modules as described in the traffic
controller idle control section. If SDRAM contents must be maintained
during the idle state, then the SDRAM self-refresh mode must be
enabled before going to chip idle (set the SLFR bit of the
EMIFF_SDRAM_CONFIG register to 1, and the RFRSH_STDBY bit
of the EMIFF_SDRAM_CONFIG2 register to 1). The self-refresh bit is
cleared every time OMAP leaves chip idle.
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Prepare for wake up by enabling and unmasking MPU interrupts.
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Ensure that all interrupts and DMA status bits have been cleared. If all
of the other idle conditions and controls have been met (as per the
MPU, DSP, TC and DPLL descriptions), then activating the
wait-for-interrupt instruction at this point leads to the full chip idle state,
allowing the reference clock to be stopped.
In chip idle mode, the MPU, the DSP, the DPLL and peripherals that use
CK_REF as their source are stopped, while the external clock source remains
the only active clock signal.
In deep sleep mode, all internal system clocks (MPU, DSP, DPLL, peripherals,
and timers) and the external reference clock source are stopped, leaving the
OMAP3 in a static state in which it consumes the lowest possible power. In this
mode, it is recommended that the WKUP_MODE bit of the ARM_IDLECT1
register be set to 0 before going into IDLE. A complete handshake between
the OMAP and external module turns off the OMAP input clock. This
handshake ensures that OMAP wakes up properly.
Any unmasked interrupt request, either to the MPU or the DSP, any DMA clock
request, or setting the L3_OCPI_EN signal to high exits the idle mode.
When the WKUP_MODE bit of ARM_IDLECT1 is set to logical 0, the wake-up
procedure can be controlled by the ULPD.
When the WKUP_MODE bit value is set to logic 1, a single wake-up condition
initiates a chip wake-up procedure. The wake-up condition can be caused by:
SPRU749A