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OMAP5912 Clock Architecture
56
Clocks
MCLK,
the
software
CLOCK_CTRL_REG.COM_MCLK_INV to select the inactive level of MCLK.
A software request for MCLK is also available. Depending on the software
request used, MCLK can be:
J
48MHz coming from the ULPD APLL (legacy support)
J
48MHz coming from the ULPD APLL divided by a programmable ratio
J
The system clock
For the system clock on MCLK with a software request, the following software
procedure must be used:
J
Set the CONF_MOD_COM_MCK_12_48_SEL_R bit to 0 in the
MOD_CONF_CTRL_0 register.
J
Set the COM_SYSCLK_PLLCLK_SEL bit to 1 in the ULPD
COM_CLK_CTRL_DIV_SEL register.
J
Set
the
DIS_COM_MCLK_REQ
SOFT_DISABLE_REQ_REG register.
J
Set
the
SOFT_COM_MCKO_REQ
SOFT_REQ_REG register.
Consequently,
the
SOFT_COM_MCKO_REQ to disable or reenable MCLK. When the system
clock is output on MCLK, the software can also use the ULPD
CLOCK_CTRL_REG.COM_MCLK_INV to select the inactive level of MCLK.
For a 48-MHz clock on MCLK with a software request (legacy support), the
following software procedure must be used:
J
Set the CONF_MOD_COM_MCK_12_48_SEL_R bit to 1 in the
MOD_CONF_CTRL_0 register.
J
Set the COM_SYSCLK_PLLCLK_SEL bit to 1 in the ULPD
COM_CLK_CTRL_DIV_SEL register.
J
Set
the
DIS_COM_MCLK_REQ
SOFT_DISABLE_REQ_REG register.
The CONF_MOD_COM_MCK_12_48_SEL_R bit acts both as selection for
48MHz on MCLK and as a request for ULPD APLL. This sends the 48-MHz
clock to MCLK. Setting DIS_COM_MCLK_REQ to 1 does not gate the output
of the APLL or the MCLK clock source selection, but it does disable the APLL
clock request associated to CONF_MOD_COM_MCK_12_48_SEL_R.
For a divided 48-MHz clock on MCLK with a software request, the following
software procedure must be used:
can
also
system
clock
is
use
the
bit
to
1
in
the
to
1
in
the
available
on
MCLK.
bit
to
0
in
the
SPRU751A
ULPD
ULPD
ULPD
Use
ULPD
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