Texas Instruments OMAP5912 Reference Manual page 735

Table 76. DMA LCD Channel Control Register (DMA_LCD_CCR) (Continued)
Bit Name
10 OMAP3_1_Compatible_
disable
9 REPEAT
8 AUTOINIT
7 ENABLE
6 PRIO
5 RESERVED
4 BS
3:0 RESERVED
SPRU755B
Function
OMAP3.1 channel compatibility control.
Repetitive operation. (Tie off = 1)
Autoinitialize at the end of the transfer. (Tie off = 1)
Enable transfer. (Tie off = 1)
Channel priority. (Tie off = 1)
Reserved
Block synchronize
Reserved
The OMAP_3.1_mode tie-off values are the values given to the bits in
OMAP3.1 compatible mode, since the DMA_LCD_CCR, DMA_LCH_CTRL,
and DMA_LCD_CSDP registers do not exist in the compatible mode. These
values are tied off/on in hardware.
bs: block synchronize
-
If the external LCD controller is the destination and bs = 1:
Then the DMA LCD channel is synchronized on blocks. This means
a block transfer is started each time the LCh is enabled and a hard-
ware synchronization signal is received from the external LCD con-
troller.
One DMA LCD channel request triggers one block transfer, in
H
both single and dual block modes.
H Two DMA LCD channel requests are required to trigger two block
transfers, even if it is in dual block mode.
If the external LCD controller is enabled and bs = 0
Then the LCD channel is a software-triggered channel. This means
a transfer can start as soon as the LCh is enabled.
If the OMAP LCD controller is the destination, the bs bit is ignored.
If auto init and repeat and/or end prog are set, a hardware request for
successive block transfers is required.
Direct Memory Access (DMA) Support
System DMA
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
rst
R/W 0
R/W ND
R/W ND
R/W ND
111