Texas Instruments OMAP5912 Reference Manual page 775

Multimedia processor device overview and architecture

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Table 107. DMA Controller Configuration Registers (Continued)

Channel 1 (Continued)

Channel 1 source element index

Channel 1 source address counter

Channel 1 destination address counter

Channel 1 destination element index

Channel 1 destination frame index

Channel 2 source destination parameters

Channel 2 control

Channel 2 interrupt control

Channel 2 status

Channel 2 source start address, lower bits

Channel 2 source start address, upper bits

Channel 2 destination start address, lower bits

Channel 2 destination start address, upper bits

Channel 2 element number

Channel 2 frame number

Channel 2 frame index

Channel 2 element index

Channel 2 source address counter

Channel 2 destination address counter

Channel 2 destination element index

Channel 2 destination frame index

Channel 3 source destination parameters

Channel 3 control

Direct Memory Access (DMA) Support

Word Address

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