Texas Instruments OMAP5912 Reference Manual page 195

Multimedia processor device overview and architecture

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OCP-T1/T2 modules are in idle mode. This can be done by setting

ARM_IDLECT3 (IDLTC1_CK) = 1 and ARM_IDLECT3 (IDLTC2_CK) = 1,

which disables the TC1_CK and TC2_CK clocks when there is no activity

and the idle request is acknowledged by the target. These modules can

also be placed in idle mode by disabling TC1_CK and TC2_CK completely

by setting EN_TC1_CK and EN_TC2_CK to 0.

The idle interface (IDLIF_ARM) bit of the ARM_IDLECT1 register is set to

The MPUI clock is idle.

There are no system DMA pending transfers.

All the TC subdomains are stopped by setting the appropriate bits in the

ARM_IDLECT2 and ARM_IDLECT3 registers.

There are no MPU or DSP interrupt requests.

Power-down enable bits PDE and PWD_EN of the EMIFS configuration

Disable the SDRAM clock and set the power-down enable bit to 1 with the

EMIFF configuration register. TC idle mode entry is affected by the

RFRSH_STBY bit of the EMIFF_SDRAM_CONFIG_2REG TC register.

When set to 1, the SDRAM must be put into self refresh state before going

idle (SLRF bit of EMIFF_CONFIG register). Every time the SDRAM wakes

up, the self-refresh state is cleared, so returning to idle requires that the

SLRF bit of EMIFF_CONFIG_REG is set to 1 again.

It is important to note that ceratin bits in the ARM_IDLECT1,2,3 registers can

prevent the chip from entering the idle state.

If the ARM_IDLECT2.EN_APICK bit is 1, you need either the

ARM_EWUPCT.REPWR_EN bit to be 0 or you need the

ARM_IDLECT3.IDLOCPI_ARM bit to be 1 to go to idle.

If ARM_IDLECT2.EN_APICK is 0, ARM_EWUPCT.REPWR_EN and

ARM_IDLECT3.IDLOCPI_ARM are don't care and will not prevent

you from going to idle.

If the EN_API_CK bit field of ARM_IDLECT2 is 1, then IDLAPI_ARM

bit field of ARM_IDLECT1 needs to be 1 to go to idle

Then the traffic controller completes its current operations and pulls the

TCIDLE_ACK signal to a high level to indicate that TC_CK can now be safely

stopped. In addition, the shut-down of the TC_CK clock indicates to the chip

idle control logic to initiate the DPLL idle.

Clock Generation and Reset Management

OMAP3.2 Subsystem

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