Texas Instruments OMAP5912 Reference Manual page 173

Table 42. EMIFF SDRAM Operation Register (EMIFF_OP) (Continued)
Bit Field
3:2 Operation mode
1:0 SDRAM type
Table 43. EMIFF SDRAM Manual Command Register (EMIFF_CMD)
Bit Field
31:4 Reserved
3:0 SDRAM
Table 44. EMIFF Dynamic Arbitration Priority Time-Out Register 1
(EMIFF_PTOR1)
Bit Field Description
31:7 Reserved Must be all 0.
7:0 DMA Number of clock cycles before DMA requests are made high
priority in the dynamic priority scheme for the EMIFF SDRAM
interface.
SPRU749A
Base Address = 0xFFFE CC00, Offset = 0x80
Description
00: Low-power/low-bandwidth mode (LPLB mode).
01: High-power/high-bandwidth mode (HPHB mode).
10: Programmable operating mode 0 (POM0 mode).
11: Reserved. Must not be used.
The type of SDRAM:
00: Regular SDR SDRAM
01: Regular DDR SDRAM
10: Low-power SDR SDRAM
11: Mobile DDR SDRAM
Base Address = 0xFFFE CC00, Offset = 0x84
Description
Must be 0000:000.
Manual command
0000: NOP command
0001: Precharge command
0010: Autorefresh command
0011: Enter deep sleep command
0100: Exit deep sleep command
0111: Set CKE signal high
1000: Set CKE signal low
1xxx: Reserved. Not for use.
Base Address = 0xFFFE CC00, Offset = 0x8C
Traffic Controller
R/W Reset
R/W
R/W
R/W Reset
R 0x0000000
R/W
R/W
R 0x000000
R/W
OMAP3.2 Subsystem
01
00
0x0
Reset
0x00
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