Texas Instruments OMAP5912 Reference Manual page 579

Table 28. Status Request Register 2 (STATUS_REQ_REG2)
Bit Name
15:1 UNUSED
0 MMC2_DPLL_REQ
Note: Bit 0 in this register reflects the state of the clock request regardless of whether it is masked or not (by the corresponding
SOFT_DISABLE_REQ_REG bit).
Table 29. Sleep Status Register (SLEEP_STATUS)
Bit Name
15:2 UNUSED
1 BIG_SLEEP
0 DEEP_SLEEP
Note: Both bits can be read at 1 in case ULPD goes from deep sleep to big sleep before the transition back to awake.
Table 30. Setup Analog Cell4 ULPD1 Register (SETUP_ANALOG_CELL4_REG)
Bit Name
15:0 SETUP_ANALOG_CELL4
Note: This setup stage is for the FSM1 of the ULPD.
Table 31. Setup Analog Cell5 ULPD1 Register (SETUP_ANALOG_CELL5_REG)
Bit Name
15:0 SETUP_ANALOG_CELL5
Note: This setup stage is for the FSM1 of the ULPD.
SPRU753A
Base Address =0xFFFE 0800, Offset = 0x54
Function
Unused
Status of the MMC2_PLL_REQ
0: Inactive
1: Active
Base Address = 0xFFFE 0800, Offset = 0x58
Function
Unused
This bit is asserted (1) when waking up from big
sleep. This bit is cleared (0) when the FSM goes
out of awake.
This bit is asserted (1) when waking up from
deep sleep. This bit is cleared (0) when the FSM
goes out of awake.
Base Address = 0xFFFE 0800, Offset = 0x5C
Function
Setup time of analog cell4 in number of sleep
clock cycles
Base Address = 0xFFFE 0800, Offset = 0x60
Function
Setup time of analog cell5 in number of
sleep clock cycles
Ultralow-Power Device
R/W Reset
R 0x0
R Unknown
R/W Reset
R 0x0
R Unknown
R Unknown
R/W
R/W
R/W Reset
R/W
Power Management
Reset
0x0
0x0
61