Texas Instruments OMAP5912 Reference Manual page 738

System DMA
Table 77. DMA LCD Control Register (DMA_LCD_CTRL) (Continued)
Bit Name
5 BUS_ERROR_IT_
COND
4 BLOCK_2_IT_COND
3 BLOCK_1_IT_COND
2 BUS_ERROR_IT_IE
1 BLOCK_IT_IE
0 BLOCK_MODE
114 Direct Memory Access (DMA) Support
Base Address = 0xFFFE E300, Offset Address = 0xC4
Function
Bus error interrupt condition.
Block 2 interrupt condition.
Block 1 interrupt condition.
Buss error interrupt enable.
Block interrupt enable.
Type of block mode used for the LCD transfer.
The DMA LCD control register contains nine bit-fields, which control the LCD
channel operation. There are two cases of interrupt: end block buffer or abort
on the bus (bus error). Bits block_it_ie and bus_error_iie (interrupt enable)
enable the generation of the interrupt.
If the status bits (xxx_cond bits and the corresponding interrupt enable bits
xxx_ie bits) are all set, an interrupt signal is sent from the DMA LCD channel
to the CPU. The CPU reads this register to find the cause of the interrupt.
Users must write to this register to clear the status bits.
BLOCK_MODE: Type of block mode used for the LCD transfer
-
0: One block buffer; only registers relative to block 1 are used.
1: Two block buffers; the LCD channel reads alternatively top_block_1 and
top_block_2.
BLOCK_IT_IE: end block interrupt enable
-
0: Interrupt disabled.
1: Interrupt enabled.
This bit enables an end of block interrupt for either block 1 or 2 when dual
block mode is selected.
BUS_ERROR_IT_IE: bus error interrupt enable
-
0: Interrupt disabled.
1: Interrupt enabled.
R/W Reset
R/W 0
(read
as 0)
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
SPRU755B