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1.4.3
Overflow/Underflow Interrupts
Overflow Interrupt Generation
SPRU760B
In slave mode, whether the functional mode is MCU DSP or DMA, the
possibility exists that the receive register (SPI_RX) is overflowing or/and the
transmit register (SPI_TX) is underflowing. In either case, an interrupt is
generated and sent to the host. It is up to the host to take the right action,
according to the received interrupt.
To generate an overflow interrupt, the SPI must be in the following state:
SPI is configured in slave mode (SPI_SET2 [15] = 0).
-
Enable for overflow interrupt is active (SPI_IER [2] = 1).
-
The receive register (SPI_RX) has not been read between two receptions.
-
To release the interrupt (nIRQ) activated by the RX overflow bit (SPI_ISR [2]),
the user has to clear the RX overflow status bit by writing a 1 in SPI_ISR [2].
SPI Master/Slave
Serial Interfaces
49
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